1. Field of the Invention
The present invention relates to a manufacturing method of a MOS (Metal-Oxide-Semiconductor) transistor, and more particularly, to a technique to improve transistor characteristics in such a way that, in a p-channel MOS transistor (referred to as pMOS, hereinafter), the change in the threshold voltage and the lowering of the drain saturation current that may occur in long-term use (negative bias temperature instability) are prevented, and, in an n-channel MOS transistor (referred to as nMOS, hereinafter), the change in the threshold voltage due to the hot electron effect is suppressed.
2. Description of the Related Art
For the generation of semiconductor devices of which, with miniaturization proceeding, the design rule is reduced to the order of deep-submicron or less, a surface channel type structure is the one that is generally employed for a pMOS with the object of controlling the short channel effect. To obtain this surface channel type structure, it is necessary to form a source-drain region with a shallow junction. For the purpose of achieving this shallow junction, then, a technique in which, instead of B.sup.+, BF.sub.2.sup.+ is utilized as an ion species in forming the source-drain region has been, hitherto, in wide use. Since BF.sub.2.sup.+ has a larger mass than B.sup.+, the range thereof can be made smaller and, consequently, a shallow junction can be attained.
When BF.sub.2.sup.+ is used, however, a phenomenon called the boron penetration is known to cause a serious problem. In a manufacturing method of a MOS transistor, both the implantation of dopants into a gate electrode and the implantation of dopants into a source-drain region are normally carried out in one common step so as to minimize the number of steps therein. In this instance, it is BF.sub.2.sup.+ that is doped into the gate electrode. The presence of fluorine, however, causes diffusion of boron within the gate electrode to be accelerated, in the step of a heat treatment for forming the source-drain region and the like so that some atoms of boron may become caught in a gate oxide film and some other atoms, penetrating through the gate oxide film, may diffuse into a silicon substrate. Once this boron diffusion occurs, the reliability of the gate oxide film is lowered, with the threshold voltage of the transistor rising and with the breakdown voltage thereof dropping and so forth. The problem of this sort arises notably in the case that the ion implantation with BF.sub.2.sup.+ which simultaneously introduces F and B is carried out. When B.sup.+, instead of BF.sub.2.sup.+, is used for the ion implantation, F cannot be caught in the gate electrode together with B. Consequently, even if diffusion of B takes place, B does not come to penetrate through the gate oxide film and, therefore, the problem as described above is hardly ever brought about.
Meanwhile, recent various improvements on the ion implantation system have enabled the ion implantation to be conducted at a low acceleration voltage and, under the current conditions, it is possible to form a shallow junction even by the implantation with boron. Therefore, with some additional considerations, such as setting the acceleration voltage low, given to the ion implantation method, the use of the implantation with boron can achieve both the formation of a shallow junction in a source-drain region and the solution of the problem of boron penetration.
Further, a technique in which both B.sup.+ and F.sup.+ are doped into a source-drain region while only B.sup.+ is doped into a gate electrode has been also developed. In Japanese Patent Application Laid-open No. 330441/1996, there is disclosed another method wherein F.sup.+ -ions are first implanted into a source-drain region and thereafter the entire surface is subjected to the ion implantation of boron. It is considered that, also by such a method, the prevention of the boron penetration, together with the formation of a shallow junction can be attained, since no fluorine is doped into a gate electrode.
As described above, in a manufacturing process in which not BF.sub.2.sup.+ but B.sup.+ is implanted into a gate electrode, the boron penetration can be well suppressed. With such a process, however, the following problems that have not been recognized so far arise.
While the region directly under a gate insulating film functions as a channel region of the transistor, terminal sections of silicon constituting this channel region are, in form, either remaining unbound (the dangling bond) or bonded to a hydrogen atom, as shown in FIG. 5(a). Because the dangling bond traps the carrier and lowers the capability of the channel region to function, the dangling bonds therein are normally eliminated, in the prior art, by carrying out the hydrogen termination through a treatment of hydrogen annealing and generating the Si--H bonds. Since the bond energy of Si--H is relatively low, however, hydrogen is liable to dissociate from the bonding in course of time, resulting in generation of the dangling bond once more. As the dangling bonds increase like this, in course of time, through the use of the transistor, the degree of carrier trapping in the channel region also increases in course of time (This phenomenon is referred to as the negative bias temperature instability effect (slow trap effect), hereinafter). Once the negative bias temperature instability effect is generated, there arises a problem that the threshold voltage changes in course of time and, along with that, the drain saturation current decreases in course of time.
Such a problem resulting from generation of the negative bias temperature instability effect has not been, up to now, recognized fully or techniques to solve this problem have been hardly studied. The present invention is made to overcome problems of this sort and its immediate object is to suppress generation of the negative bias temperature instability effect and prevent the change in threshold voltage and the decrease in drain saturation current.
Further, another object of the present invention is to overcome the problem of deterioration of element characteristics that arise due to the hot electron effect. The hot electron effect is a phenomenon in which high energy electrons produced by being accelerated by the electric field between source and drain together with electrons and holes produced by the impact ionization intrude into a gate oxide film and thereby alters the MOS characteristics. In a conventional MOSFET (MOS Field Effect Transistor), silicon in a channel region has the terminal structure of Si--H with a weak bonding strength so that, in operating the transistor, channel carriers are liable to collide with and break the Si--H bonds. Such breaking of the Si--H bonds leads to the generation of an interface state, which then brings about the hot electron effect. The hot electron effect causes the threshold voltage to change and the mutual conductance g.sub.m to degrade and, thus, reduces the reliability of the element greatly. This problem is particularly pronounced in the nMOS, because a larger drain saturation current flows in the nMOS than the one in the pMOS. Further, the hot electron effect becomes more marked when the gate length becomes shortened through the element miniaturization, or a high electron field becomes applied between source and drain. It is another object of the present invention that such a problem is solved and the change in the threshold voltage as well as the degradation of the mutual conductance g.sub.m that occur due to the hot electron effect are prevented with effect.
Further, although both the suppression of the negative bias temperature instability effect and the suppression of the hot electron effect cause the same effect of preventing the change in the threshold voltage, these are essentially different issues. The change in the threshold voltage due to the negative bias temperature instability effect is brought about by gradual breaking of the Si--H bonds in a channel region and generating the dangling bonds in course of time and is an issue concerning an improvement on the long term reliability of the transistor. On the other hand, the change in the threshold voltage due to the hot electron effect is brought about through intrusion into a gate oxide film by hot electrons which are generated when the transistor is in use. In short, they are separate issues originated through different mechanisms at different places.
As described above, the present invention aims to solve the first problem that the change in the threshold voltage and the decrease in the drain saturation current due to the generation of the negative bias temperature instability effect should be prevented, and further to solve the second problem that, by suppressing the hot electron effect, the change in the threshold voltage and the degradation of the mutual conductance g.sub.m should be prevented. Especially when the present invention is applied to a pMOS, the primary object is to solve the problem of the negative bias temperature instability effect and when applied to an nMOS, the problem of the hot electron effect. The explanation lies in the fact that, in a pMOS, ON-current is considerably small so that the problem of hot electrons occur relatively infrequently and the problem of the negative bias temperature instability effect becomes more important, while in an nMOS, in contrast with that, the problem of hot electrons becomes more important. In a pMOS, negative bias is applied on a gate electrode. Therefore holes which can generate dangling bonds are introduced to the region under the gate electrode and the problem of the negative bias temperature instability effect becomes more important in a pMOS.